A 70cm Wide-band Transceiver Concept

Martin Liebeck, DL2ZBN @ DB0GV, Helfmannstr. 16, 64293 Darmstadt
Alexander Kurpiers, DL8AAU @ DB0ZDF, Ludwigshöhstr. 77, 64285 Darmstadt


This article presents a description of a 70cm wideband transceiver for duplex operation. The modules are designed for operation in a 200 kHz wide duplex channel, freely selectable from 430-440 MHz with a 100 kHz channel spacing. First prototypes were introduced on the international Packet Radio Symposium in April 1997. Some minor changes resulting from further experience were added to the text since then.

1 High-speed Packet Radio - Why do we need it?

Narrow-band packet radio net access frequencies with 25kHz channel spacing for operation with either 1k2 Baud AFSK or 9k6 Baud FSK are state-of-the-art and standard for over 15 years now. They are common in wide areas of Europe.

These transmission speeds are sufficient for connecting local BBS systems, taking part in packet radio conversation groups or accessing DX clusters. There are, however, new emerging applications requiring higher transmission speeds. These requirements ask for higher speeds of one order of magnitude compared to the standard 9k6 Baud operation.

Examples for such applications are new BBS systes with HTML graphical user interfaces, digital voice transmission or image transmission in real-time following the ISDN standard. Inter-node links following those requirements are currently being set up. High-speed user accesses to the packet radio network are still missing.

2 Technical Requirements

In Germany, there is currently a single 70cm packet radio channel assigned for user accesses with a bandwidth of 200kHz. This channel has experimental status and the assignment of further channels cannot be foreseen. Therefore, the user TRX is designed as a single channel version without any user interface for changing the frequency. The frequency however, should be changeable through re-programming. The transceiver must be adaptable to be used either as part of a digipeater or a user station.

To utilise the benefits of high-speed operation, the transmit/receive delay should be smaller than 1 ms. The S/N at the receiver has to be 10 dB higher due to a wider bandwidth, if the access area requirements are similar to 9k6 operation. This can be achieved by either increasing the transmit power by 10dB or the utilisation of an appropriate antenna gain.

For user operation in unfavourable locations and on digipeaters, the authors recommend an output power of 20 Watts. From experience, lower output power may be sufficient. Therefore, an alternative power amplifier is presented with an output power of 2-7 Watts.

In summary, the requirements are:

Baudrate76k8 to 115k2
Modulation Bandwidth100Hz - 80kHz
TX/RX delay<1ms
Channels1, digipeater or user mode selectable
Output power20 Watts, alternatively 2-7 Watts
DC voltage12 Volts
A transceiver concept was presented in [2] that meets the above requirements. First experience with prototypes and problems with parts availability and parts cost led to some minor design changes.

The Concept

The transmitter FSK signal is generated by modulating a VCO which is stabilised through a slow PLL to a frequency. The loop filter of the PLL has a cut-off frequency of 40Hz, resulting in a minimum bit rate of 38k4 Baud. This slow PLL can only compensate for long-term drift caused by temperature- and ageing effects. Reactions, resulting from switching between TX and RX, have to be avoided. Therefore, a few buffer stages were added between the oscillator and the first switched stage. Also, the power supply of the individual stages has to be well decoupled. This can only be achieved with moderate efforts if the concept is divided in three separate modules: receiver, transmitter and power amplifier, all in separate boxes. Only the power amplifier is switched between transmit and receive phases.

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Figure 1: Block diagram of the transceiver concept

Figure 1 shows the three blocks. Receiver, transmitter and the 7 Watts power amplifier are accommodated in tinned steel boxes of size 74 x 111 x 35 mm. The 20 Watts power amplifier is accommodated in a cast aluminium box with an attached heat sink, 120 x 95 x 34 mm in size.

4 Realisation

4.1 Transmitter

The transmitter uses similar as in [1] a VCO operating on the output frequency. It uses a BF 979 transistor and a 20mm piece of semi-rigid cable as the oscillator inductance. The VCO is stabilised by the Siemens PLL circuit SDA 3302-5 and the VCO loop frequency is 40 Hz. The SDA 3302 uses a fixed-ratio divider for the loop reference frequency and channel spacing of 100 kHz results with a 6.4 MHz crystal. The PLL can be programmed according to the 100 kHz channel spacing.

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Fig. 2: Block diagram of the transmitter

The PLL circuit can be programmed through an I2C-bus with a PIC12C508 by Arizona Microchip. A file for programming this chip is available. This 8-pin DIL RISC processor has an internal reset logic and an internal RC oscillator for clock generation.

The prototypes showed that this internal reset circuit operates at severe reductions in the supply voltage. The PIC-processor operates down to voltages as low as 3 Volts, but the PLL circuit looses its memory. To avoid the transmitter operation on unintended frequencies, an external reset circuit was added which senses even small reductions in the supply voltage and reprogrammes the PLL circuit.

Four frequency telegrams with different chip addresses are sent from the PIC to the PLL IC over the I2C-bus if a reset is applied. These telegrams cover all combinations of RX and TX frequencies in user or digipeater mode. A Jumper on the address select pin of the SDA 3302 selects its chip address and chooses the right frequency telegram.

A BF960 dual gate MOSfet is coupled to the VCO as a buffer. It was selected because of its low feedback effects from its output to its input, exhibiting an S|12|^2 of smaller than -40 dB). 3 dBm of output power can be achieved at this stage.

Two further buffer stages using BF960s increase the VCO frequency stability when the output load changes. Each stage has a gain of 11dB. In order to achieve an output power of 10dBm and a further decoupling, two 7dB attenuators are used. They also reduce matching losses.

A good decoupling of the power supply is done by using three voltage controllers; one 78L05 for PLL and PIC, one 78L09 for the oscillator and the first buffer and another 78L09 for both BFR90.

A further filtering of the power supply is done by R10, C22, C7 and C29 to assure low phase noise. On a spectrum analyser the noise spectrum is so reduced by another -20 dB 100 kHz from the carrier frequency.

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Fig. 3: Circuit diagram of the transmitter

4.1.1 Construction

The PC board is made of standard 1.5 mm two-sided epoxy-glass material. The upper side is fully copper clad and privides a shielded surface acting as an RF groundplane. The interconnection tracks are etched to the reverse side. Components (except SMD) are shielding of the semi-rigid cable is soldered to the ground plane of the PC board. Both BFR90 are mounted with their printed side facing downwards. The printed sides of both BF979 and BF960 are facing upwards (to the ground PC board plane). The drain connector of the BF960 is longer than the other connectors. The source connector of the BF960 should be soldered to the ground plane as short as possible if the PC board is not through-plated. Do not use a socket for the SDA3302-5.

The connector for the signal output of the transmitter can be BNC. In this case, the central pin of the BNC connector can be connected with a "flying" capacitor C13 due to mechanical constraints imposed by the BNC connector. Also usable is a SMA or SMB connector, where the central pin can be soldered directly to the PC board. C13 has to be placed on the board in this case.

4.1.2 Alignment

Frequency measurements can be done using test points 2 and 3. For this, the PLL IC has to be switched to a test mode which is done by adding a 330 Ohm resistor to the lower part of the PC board between pin 7 of the PIC and ground. This resistor is designated as R_test. Do not forget to remove the resistor after the measurement.

Next, the jumper JP1 is set to decide whether the transmitter will be used as part of a user station or a digipeater. For user operation, the jumper is not set, in digipeater mode, it has to be set. If the supply voltage is applied, the PLL IC will be set by the PIC. If the PLL cannot be programmed by the PIC, the LED D2 will come on. If all goes well, D2 will only come on for a split second.

TP2 has the phase reference frequency of the PLL in form of a digital TTL signal. C24 should be set such that the frequency of this signal is 12.5 kHz. Do not try to measure the frequency of the 6.4 MHz oscillator directly. It operates in serial resonance and the probe would change its frequency.

TP1 shows the control voltage of the PLL. When the sky trimmer C10 is tuned slowly (!) this voltage should be adjustable to 4 to 5 volts. The trimmer should then be about in centre position. Is the control voltage around 9 volts, the VCO frequency is too low and C10's capacitance has to be lowered. If it is around 0 volts, the capacitance has to be increased. With this, all adjustments on the TX module are done.

TP3 shows the VCO frequency divided by the PLL IC. It also shows a frequency of 12.5 kHz if the PLL is locked. TP3 is not necessary for tuning the TX module but it can help for eventually necessary fault detection. Even without a 500 MHz counter, you can see whether the VCO operates. The dividing factor for the frequency 434.900 MHz (user frequency in Germany) is 34792.

For achieving at least -40 dB at the channel edges of the output spectrum, the frequency shift must not be greater than 25-30 kHz at 76k8. To avoid adjacent channel interference, the modulation voltage leaving the modem should not exceed 500mVss.

Our prototypes showed typical collector and drain voltages of:
The output power of all TX modules was minimum 10 mW.

4.2 Receiver

The front stage uses an HP AT41586 bipolar transistor. The achievable noise figure is acceptable and the front end can handle very strong signals as well. Mirror frequencies are suppressed by a 3-pole helix filter.

For reasons of large signal handling capability we intended to use a TV tuner IC. A TDA5030 is used in [1] but is unavailable as it is not produced anymore. Alternatively. the TDA5331 has a mixer input with an impedance close to 50 Ohms and an output matched for a SAW filter. Both features are well-suited for our design.

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Figure 4: Block diagram of the receiver

The symmetrically constructed oscillator of the TDA5331 is PLL stabilised. As well as in the receiver an SDA3302-5 is used for this purpose. This concept is more flexible and cheaper than standard solution with a crystal and a frequency tripling stage. The first prototype used only on PIC in the transmitter which also programmed and controlled the PLL in the receiver. As it turned out, an extra PIC12C508 is cheaper than 4 feed-through capacitors needed for transferring the I2C bus from the transmitter to the receiver.

Therefore, the receiver also has a PIC. After programming the PLL IC, the PIC switched to a sleep mode and the processor clock signal is switched off. Interference with the receiver is therefore unlikely.

A bigger problem is posed by the selection of a suitable filter for the first IF with about 200 kHz bandwidth. After a long data sheet search we came across an SAW filter with 41.7 MHz centre frequency and a bandwidth of 300 kHz. Unfortunately, this filter is too expensive.

Contrary to [2] and [3], we use the much cheaper filter TFS80B with 80 MHz centre frequency. The necessary changes for doing this were kept to a minimum by the flexible concept.

An IF of 455 kHz is not suitable because of the required bandwidth. An IF of 10.7 MHz offers several ceramic filters for FM radio applications which have suitable bandwidths and group delay times. A Phillips SA626 is selected for the second IF stage. It can directly handle a ceramic filter with an impedance of 330 Ohms and also contains an oscillator, a mixer, a limiter amplifier, an FM demodulator and a fast RSSI (received signal strength indicator) output. This is used together with an adjustable comparator as a DCD.

Analogue to the transmitter, the individual stages are supplied with power through their own regulator circuits to avoid signal coupling.

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Figure 5: Circuit diagram of the receiver 1/2

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Figure 6: Circuit diagram of the receiver 2/2


The hints given in the transmitter sections are similarly valid for the construction of the receiver. For L5, 2.5 turns of 1mm silver plated wire (5mm coil diameter) are used. Inserting the SMD IC's requires a little bit of skill. It is best done with a hot soldering iron, a fine iron tip and fine solder (the thinner, the better). The base lead of the AT41586 is bevelled. In case the two planes of the double clad PC board are not interconnected by plated-through holes, the emitter connectors have to be soldered to the ground plane by using two hollow rivets.


As well as the transmitter, the receiver is almost without tuning. The designation of the test points is analogue to the transmitter with the exception that there is no trimmer for adjusting the VCO. The frequency is adjusted by changing L5 instead. Is the control voltage at TP1 9 volts, the frequency of the VCO is loo low. The coil hast to be slightly expanded in this case or even to be cut. If it is close to 0 volts, it has to be compressed or a longer coil has to be inserted. After a successful tuning, the voltage should be between 4 and 5 volts. The oscillator operates 80 MHz below the receiver frequency.

The demodulator circuit Fi5 should be tuned with an oscilloscope connected to the AF output to maximum and best noise "symmetry". This has to be done without a receiver input signal. With a weak input signal coming e.g. from the accordingly jumpered transmitter module without antenna, Fi1 and L2 are tuned to a maximum output signal at the RSSI output. Sometimes even the input noise without a signal is sufficient to do the tuning. Without an input signal the RSSI output should show about 350 to 450 mV. This voltage may vary with SA626's from different batches. At last, R23 is tuned such that the DCD output without an input signal is just still "low".

20W Power Amplifier

The power amplifier is similarly as in [1] built around a 20 Watt hybrid power module. These modules are offered by various manufacturers and can often be obtained second hand of amateur rallies. Most hybrid modules require an input power of 20 dBm. Therefore, there is a driver stage before the hybrid module input. Furthermore, the PA module takes care of the TX/RX switching and suppresses output harmonics through a filter.

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Figure 7: Circuit diagram 20W Power Amplifier

4.3.1 Construction

As almost all components are SMD, the use of hollow rivets is unavoidable if the ground plane on one side and the ground tracks on the other side of the PC board is not interconnected. The transistor BUZ171 has to be mounted vertically, with its printing facing the module. The printing of the BFR91 is visible form the component side. The coil L1 consists of 9 windings of 1mm silver plated copper wire, wound 5mm in diameter.

Even for applications in duplex systems without an antenna switch the transmitter should be equipped with a low-pass filter. This filter is designed to reduce the level of harmonics. The diode D1 can in this case be replaced by a capacitor of 1nF and diodes D2 and D3, as well as capacitors C17 to C20 and components R6, R7, L1, C9, can be omitted.

As hybrid power modules show a rather moderate efficiency, mounting the module to a heat sink is very important. Consider that for digipeater operation, the duty-cycle is nearly 100%. Carefully fit the amplifier board to a heat sink and position the module to it. Check if it fits properly, then remove the module and smear a thin, uniform layer of heatsink compound on the mating face of its metal flange, but do not use heat sink compound if the module has no ground separate connectors to the PC board.

4.3.2 Alignment

Just apply power and see if the amplifier is working. There are no tunable parts.

2-7 Watts Amplifier

The power amplifier is built around the 7 Watts linear module M57797MA by Mitsubishi. As the power delivered to the module (10 dBm) is insufficient, an additional driver stage wit a BFR91 was added. As well as in the previously described amplifier, there is an antenna switch as well as a low-pass filter.
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Figure 8: Circuit diagram 2-7 Watts Amplifier

4.4.1 Construction

The amplifier uses almost exclusively SMD components. This allows to have a continuous mass plane on the back of the PC board which helps mounting the board directly on the heat sink.

All components are mounted on the top side of the PC board. This applies also to the few conventional parts like T1, IC2, L2, L3 and R9. C15 and R8 are wired directly; C15 to the centre pin of the BNC socket and R8 from the centre pin to the tinned metal box surface.

L1 consists of 9 turns of 1mm silver wire with a coil diameter of 5mm. The coil should be wound as tight as possible, but without the windings touching each other. The printing of the transistor BFR91 faces upwards. Do not use heat sink compound, as the modul flange is the only ground connection.

4.4.2 Alignment

The power amplifier has only one tunable part - R9. This variable resistor allows the output power to be adjusted between 2 and 7 Watts. In the case of our prototype, the maximum output power was 10 Watts.

5 Wiring up

For digipeater operation you need an additional duplexer. Suitable duplexers in sometimes surprisingly good quality are available on the surplus market. They are also sold as new parts by professional retailers. In this case the price is in the order of the rest of the system.

For duplex operation you should use doubly-shielded coaxial cable to avoid signal cross coupling. RG223 or RG214 cables are a good choice.

To complement the system on the user side, you need a modem and an interface to your computer. Data rates beyond 19k2 are too much for the standard TNC2 in host mode and with TF software. Similarly is the behaviour of the interface plug-in modems like PICPAR or PAR96. The only sensible hardware solutions at the moment are RMNC and TNC3. A software alternative is the the EPP modemadapter [4], which is available from Baycom.

6 Summary

A final acknowledgement for valuable hints goes out to Wolf-Henning Rech, DF9IC and to Michael Scharfe, DK7UX for this translation.

7 Errata

Transmitter Voltage Regulator U2

Unfortunately, there is a bug in the layout. Input and output port of U2 in the transmitter are mixed up. U2 is the 78L09 providing both BFR90 with 9 Volt. Remedy: Turn the middle pin of the 78L09 (GND) to the wrong direction an mount the voltage regulator 180° against the direction shown in the component layout.

Transmitter Transistor Drills

In the transmitter, parts of the layout might be interconnected with the groundplane due to the 4 drills for the transistors. Use a drill or a file to remove the interconnection.

Ground-Pad of C5 in the 7W-Linear

One some boards of the 7W-linear provided by Gigatech, the ground-pad of C5 might not be connected to Ground. Just connect it to the nearby Grounplane.


A Literatur

[1] Bloch, M., DF2VO; Sessler, P., DF3VI; Rech, W.-H., DF9IC: 70-cm-FM-Baugruppen für Duplex-Digis und Phonie-Relais, ADACOM Magazin 5, S. 11-30, 1993.

[2] Liebeck, M., DL2ZBN; Kurpiers, A., DL8AAU: Hochgeschwindigkeits Packet-Radio - ein Transceiverkonzept für das 70cm-Band, Skriptum 13. Internationale Packet-Radio Tagung, Darmstadt 1997, S. 35-45.

[3] Liebeck, M., DL2ZBN; Kurpiers, A., DL8AAU: Hochgeschwindigkeits Packet-Radio - Baugruppen für das 70cm-Band, ADACOM Magazin 10, S. 7-22, 1997.

[4] Rech, W.-H., DF9IC, et al: Ein Modemadapter für den EPP, Skriptum 13. Internationale Packet-Radio Tagung, Darmstadt 1997, S. 46-51.

B Partlist

C Component Layout

Copyright © 1998
This Page was created by DL2ZBN on Thursday, 23. July 1998
Most recent revision Sunday, 13. September 1998